The present invention relates generally to nonvolatile semiconductor memory devices, and, more particularly, to controlling the wordline voltage in nonvolatile memory devices.
Nonvolatile memory devices retain data stored therein even if there is no power. Among nonvolatile memories, a flash memory has a function of electrically and collectively erasing data of cells. Therefore, flash memories are widely used for computers and memory cards.
Flash memories may be divided into NOR flash memories and NAND flash memories in accordance with the connection state between cells and bit lines. In general, because a NOR flash memory typically has high current consumption, the NOR flash memory may be less advantageous to high integration but may provide high speed. Because the NAND flash memory generally uses smaller cell current than the NOR flash memory, the NAND flash memory may be advantageous to high integration.
FIG. 1 illustrates the structure of a memory cell array 110 of a conventional NAND flash memory. FIG. 1 illustrates the structure of a block among a plurality of memory cell blocks included in the memory cell array 110.
Referring to FIG. 1, the NAND flash memory includes the memory cell array 110 as a storage region for storing information. The memory cell array 110 consists of a plurality of blocks and each block consists of a plurality of cell strings (sometimes referred to as NAND strings). Pluralities of floating gate transistors M0 to M31 are included in each of the cell strings. The plurality of floating gate transistors M0 to M31 are serially connected between a string selection transistor SST and a ground selection transistor GST arranged in each of the strings. A plurality of wordlines WL0 to WL31 are arranged so as to cross the NAND strings. The respective wordlines WL0 to WL31 are connected to the control gates of the floating gate transistors M0 to M31 corresponding to the respective NAND strings. A programming/reading voltage is applied through the wordlines WL0 to WL31 such that data is programmed/read to/from the corresponding floating gate transistors M0 to M31.
A page buffer circuit is provided in the flash memory to store data in the memory cell array 110 or to read data from the memory cell array 110. As is generally well known, the memory cells of the NAND flash memory may be erased or programmed using a Fowler-Nordheim tunneling current. Methods of erasing and programming a NAND flash electrically erasable and programmable read only memory (EEPROM) are disclosed in U.S. Pat. No. 5,473,563 entitled “Nonvolatile Semiconductor Memory,” and in U.S. Pat. No. 5,696,717 entitled “Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase/Program Threshold Voltage Verification Capability.”
FIG. 2 illustrates change in a wordline voltage according to a conventional programming method. To correctly control dispersion of threshold voltages of flash memory cells, the flash memory cells are programmed by an incremental step pulse programming (ISPP) method. A circuit for generating a program voltage in accordance with the ISPP method is disclosed in U.S. Pat. No. 5,642,309 under the title “Auto-Program Circuit in a Nonvolatile Semiconductor Memory Device.”
A program voltage Vpgm in accordance with the ISPP programming method sequentially increases as program loops of a program cycle are repeated as illustrated in FIG. 2. Each program loop consists of a program period and a program verification period. The program voltage Vpgm increases by a predetermined increment ΔVpgm from a predetermined initial program voltage every program loop. The program voltage Vpgm applied to the respective wordlines WL0 to WL31 is maintained uniformly with respect to the program loops.
However, because the equal program voltage Vpgm is applied to the wordlines WL0 to WL31 regardless of the structural characteristics of the wordlines, program time increases. For example, in the outermost transistors M0 and M31 among the plurality of floating gate transistors M0 to M31 included in each of the memory cell blocks, the coupling ratio of the floating gates is typically smaller than the coupling ratio of the floating gates in the other transistors M1 to M30 due to the structure of the memory cell array. Therefore, the outermost transistors M0 and M31 typically require more program loops than the other wordlines M1 to M30. Such an increase in the program loops may cause an increase in the program time such that the performance of the flash memory device may deteriorate.